mirror of
https://github.com/YosysHQ/yosys
synced 2026-02-08 18:19:46 +00:00
11 lines
478 B
Text
11 lines
478 B
Text
read_verilog mul_unsigned.v
|
|
hierarchy -top mul_unsigned
|
|
proc
|
|
|
|
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd mul_unsigned # Constrain all select calls below inside the top module
|
|
select -assert-count 1 t:BUFG
|
|
select -assert-count 1 t:DSP48E1
|
|
select -assert-count 30 t:FFRE
|
|
select -assert-none t:DSP48E1 t:FFRE t:BUFG %% t:* %D
|