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Code
Activity
1dd156f516
yosys
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passes
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Clifford Wolf
0eaab6cd1d
Add missing <deque> include (MSVC build fix)
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 15:21:59 +02:00
..
cmds
Include module name for area summary stats
2018-06-18 17:29:01 -07:00
equiv
Improve log messages in equiv_make
2018-01-19 16:20:40 +01:00
fsm
Remove some dead code from fsm_map
2017-08-21 15:02:16 +02:00
hierarchy
Add automatic verific import in hierarchy command
2018-06-20 23:45:01 +02:00
memory
Disable memory_dff for initialized FFs
2018-05-28 17:16:15 +02:00
opt
Add optimization of tristate buffer with constant control input
2018-05-12 15:18:27 +02:00
proc
Add warnings for driver-driver conflicts between FFs (and other cells) and constants
2017-12-12 17:13:27 +01:00
sat
Add async2sync pass
2018-07-19 15:31:12 +02:00
techmap
Add missing <deque> include (MSVC build fix)
2018-07-22 15:21:59 +02:00
tests
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00