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Code Activity
yosys/techlibs/xilinx
History
Eddie Hung 1da0909662 Remove SRL16/32 from cells_xtra
2019-02-28 13:56:45 -08:00
..
tests Improved xilinx "bram1" test 2015-04-09 17:12:12 +02:00
.gitignore
arith_map.v Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
brams.txt Added read-enable to memory model 2015-09-25 12:23:11 +02:00
brams_bb.v
brams_init.py Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
brams_map.v Added read-enable to memory model 2015-09-25 12:23:11 +02:00
cells_map.v Fix SRL16/32 techmap off-by-one 2019-02-28 13:56:00 -08:00
cells_sim.v Add SRL16 and SRL32 sim models 2019-02-28 13:56:22 -08:00
cells_xtra.sh Remove SRL16/32 from cells_xtra 2019-02-28 13:56:45 -08:00
cells_xtra.v Remove SRL16/32 from cells_xtra 2019-02-28 13:56:45 -08:00
drams.txt
drams_map.v
lut2lut.v Add techlibs/xilinx/lut2lut.v 2017-07-10 12:09:05 +02:00
Makefile.inc Add Xilinx RAM64X1D and RAM128X1D simulation models 2018-03-07 17:31:48 +01:00
synth_xilinx.cc synth_xilinx to call shregmap with enable support 2019-02-28 11:17:13 -08:00