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1d5f3fe506
This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.
11 lines
138 B
Verilog
11 lines
138 B
Verilog
module top(x);
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generate
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if (1) begin : blk
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wire x;
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assign x = 0;
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end
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endgenerate
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output wire x;
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assign x = blk.x;
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endmodule
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