mirror of
https://github.com/YosysHQ/yosys
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69 lines
No EOL
2.3 KiB
Systemverilog
69 lines
No EOL
2.3 KiB
Systemverilog
/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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`define PARAMS_INIT_LSRAM \
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.INIT0(slice_init_LSRAM(00)), \
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.INIT1(slice_init_LSRAM(01)), \
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.INIT2(slice_init_LSRAM(02)), \
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.INIT3(slice_init_LSRAM(03)), \
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.INIT4(slice_init_LSRAM(04)), \
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.INIT5(slice_init_LSRAM(05)), \
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.INIT6(slice_init_LSRAM(06)), \
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.INIT7(slice_init_LSRAM(07)), \
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.INIT8(slice_init_LSRAM(08)), \
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.INIT9(slice_init_LSRAM(09)), \
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.INIT10(slice_init_LSRAM(10)), \
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.INIT11(slice_init_LSRAM(11)), \
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.INIT12(slice_init_LSRAM(12)), \
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.INIT13(slice_init_LSRAM(13)), \
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.INIT14(slice_init_LSRAM(14)), \
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.INIT15(slice_init_LSRAM(15)), \
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.INIT16(slice_init_LSRAM(16)), \
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.INIT17(slice_init_LSRAM(17)), \
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.INIT18(slice_init_LSRAM(18)), \
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.INIT19(slice_init_LSRAM(19))
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`define PARAMS_INIT_uSRAM \
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.INIT0(slice_init_uSRAM(00)), \
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.INIT1(slice_init_uSRAM(01)), \
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.INIT2(slice_init_uSRAM(02)), \
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.INIT3(slice_init_uSRAM(03)), \
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.INIT4(slice_init_uSRAM(04)), \
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.INIT5(slice_init_uSRAM(05)), \
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.INIT6(slice_init_uSRAM(06)), \
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.INIT7(slice_init_uSRAM(07)), \
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.INIT8(slice_init_uSRAM(08)), \
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.INIT9(slice_init_uSRAM(09)), \
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.INIT10(slice_init_uSRAM(10)), \
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.INIT11(slice_init_uSRAM(11)) \
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// Helper function for initializing the LSRAM
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function [1023:0] slice_init_LSRAM;
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input integer slice_idx;
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integer i;
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for (i = 0; i < 1024; i = i + 1)
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slice_init_LSRAM[i] = INIT[(slice_idx * 1024 + i)];
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endfunction
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// Helper function for initializing the uSRAM
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function [63:0] slice_init_uSRAM;
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input integer slice_idx;
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integer i;
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for (i = 0; i < 64; i = i + 1)
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slice_init_uSRAM[i] = INIT[(slice_idx * 64 + i)];
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endfunction |