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https://github.com/YosysHQ/yosys
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72 lines
1.5 KiB
Text
72 lines
1.5 KiB
Text
read_verilog <<EOT
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module sim_add4(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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sat -set a 1 -set b 2 -set c 3 -set d 4 -prove y 10
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sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
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sat -set a 255 -set b 1 -set c 0 -set d 0 -prove y 0
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sat -set a 100 -set b 50 -set c 25 -set d 25 -prove y 200
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sat -set a 255 -set b 255 -set c 255 -set d 255 -prove y 252
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design -reset
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read_verilog <<EOT
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module sim_sub_mixed(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b - c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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sat -set a 10 -set b 20 -set c 5 -set d 3 -prove y 28
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sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
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sat -set a 100 -set b 50 -set c 30 -set d 10 -prove y 130
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sat -set a 1 -set b 1 -set c 255 -set d 1 -prove y 4
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design -reset
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read_verilog <<EOT
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module sim_sub_all(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a - b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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sat -set a 100 -set b 10 -set c 20 -set d 30 -prove y 40
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sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
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sat -set a 255 -set b 1 -set c 1 -set d 1 -prove y 252
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design -reset
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read_verilog <<EOT
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module sim_double_neg(
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input [7:0] a, b, c,
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output [7:0] y
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);
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wire [7:0] ab = a - b;
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assign y = c - ab;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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csa_tree
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sat -set a 30 -set b 20 -set c 10 -prove y 0
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sat -set a 50 -set b 25 -set c 100 -prove y 75
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sat -set a 0 -set b 0 -set c 0 -prove y 0
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sat -set a 255 -set b 1 -set c 1 -prove y 3
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design -reset
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