mirror of
https://github.com/YosysHQ/yosys
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178 lines
2.9 KiB
Text
178 lines
2.9 KiB
Text
read_verilog <<EOT
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module equiv_add3(
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input [3:0] a, b, c,
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output [3:0] y
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);
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assign y = a + b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_add4(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_add5(
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input [3:0] a, b, c, d, e,
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output [3:0] y
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);
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assign y = a + b + c + d + e;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_add8(
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input [3:0] a, b, c, d, e, f, g, h,
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output [3:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_signed(
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input signed [3:0] a, b, c, d,
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output signed [5:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_mixed(
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input [1:0] a,
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input [3:0] b,
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input [5:0] c,
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output [5:0] y
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);
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assign y = a + b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_sub_mixed(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b - c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_sub_all(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a - b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_sub_3op(
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input [3:0] a, b, c,
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output [3:0] y
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);
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assign y = a - b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_sub_signed(
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input signed [3:0] a, b, c, d,
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output signed [5:0] y
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);
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assign y = a + b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_double_neg(
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input [3:0] a, b, c,
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output [3:0] y
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);
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wire [3:0] ab = a - b;
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assign y = c - ab;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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