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yosys/techlibs/xilinx
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Eddie Hung e273ed5275 Wrap SRL{16,32} too
2019-08-20 15:09:38 -07:00
..
tests
.gitignore
abc_map.v Wrap SRL{16,32} too 2019-08-20 15:09:38 -07:00
abc_model.v Wrap SRL{16,32} too 2019-08-20 15:09:38 -07:00
abc_unmap.v Wrap SRL{16,32} too 2019-08-20 15:09:38 -07:00
abc_xc7.box Wrap LUTRAMs in order to capture comb/seq behaviour 2019-08-20 14:49:11 -07:00
abc_xc7.lut
abc_xc7_nowide.lut Add _nowide variants of LUT libraries in -nowidelut flows 2019-06-26 10:23:29 -07:00
arith_map.v
brams_init.py synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
cells_map.v Use abc_{map,unmap,model}.v 2019-08-20 12:39:11 -07:00
cells_sim.v Wrap LUTRAMs in order to capture comb/seq behaviour 2019-08-20 14:49:11 -07:00
cells_xtra.sh
cells_xtra.v
drams.txt
drams_map.v
ff_map.v xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado. 2019-07-11 21:13:12 +02:00
lut_map.v
Makefile.inc Use abc_{map,unmap,model}.v 2019-08-20 12:39:11 -07:00
mux_map.v
synth_xilinx.cc Remove -icells 2019-08-20 12:41:11 -07:00
xc6s_brams.txt synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc6s_brams_bb.v synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc6s_brams_map.v RST -> RSTBRST for RAMB8BWER 2019-07-29 16:05:44 -07:00
xc7_brams.txt synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc7_brams_bb.v Add BRAM arrival times 2019-08-19 12:46:35 -07:00
xc7_brams_map.v synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00