mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
d738b2c127
- Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
27 lines
384 B
Plaintext
27 lines
384 B
Plaintext
logger -expect-no-warnings
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read_verilog -sv <<EOF
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module Module;
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parameter X;
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endmodule
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EOF
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design -reset
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logger -expect-no-warnings
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read_verilog -sv <<EOF
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module Module #(
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parameter X
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);
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endmodule
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EOF
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design -reset
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logger -expect error "Parameter defaults can only be omitted in SystemVerilog mode!" 1
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read_verilog <<EOF
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module Module #(
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parameter X
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);
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endmodule
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EOF
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