yosys/tests/verilog/genblk_port_decl.ys at 1b25e1cee00a3d73ab42706684860f476bbb813e - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 01:24:10 +00:00

Zachary Snow 1d5f3fe506 verlog: allow shadowing module ports within generate blocks

This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.

2021-02-07 11:48:39 -05:00

13 lines

272 B

Plaintext

Raw Blame History

 logger -expect error "Cannot declare module port `\\x' within a generate block\." 1
 read_verilog <<EOT
 module top(x);
     generate
         if (1) begin : blk
             output wire x;
             assign x = 1;
         end
     endgenerate
     output wire x;
 endmodule
 EOT