yosys/tests/verilog/asgn_expr_not_sv_2.ys at 1b25e1cee00a3d73ab42706684860f476bbb813e - mirrors/yosys - Libre-Chip.org

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Zachary Snow 4edb1a1921 sv: support assignments within expressions

- Add support for assignments within expressions, e.g., `x[y++] = z;` or
  `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
  by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
  behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
  statements.

2023-09-05 22:27:55 -04:00

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 logger -expect error "Assignments within expressions are only supported in SystemVerilog mode." 1
 read_verilog <<EOF
 module top;
 integer x, y;
 initial y = x++;
 endmodule
 EOF