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https://github.com/YosysHQ/yosys
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7b74caa5db
The previous version could easily generate a large amount of padding when the constant factor was significantly larger than the width of the shift data input. This could lead to huge amounts of logic being generated before then being optimized away at a huge performance and memory cost. Additionally and more critically, when the input width was not a multiple of the constant factor, the input data was padded with 'x bits to such a multiple before interspersing the 'x padding needed to align the selectable windows to power-of-two offsets. Such a final padding would not be correct for shifts besides $shiftx, and the previous version did attempt to remove that final padding at the end so that the native zero/sign/x-extension behavior of the shift cell would be used, but since the last selectable window also got power-of-two padding appended after the padding the code is trying to remove got added, it did not actually fully remove it in some cases. I changed the code to only add 'x padding between selectable windows, leaving the last selectable window unpadded. This omits the need to add final padding to a multiple of the constant factor in the first place. In turn, that means the only 'x bits added are actually impossible to select. As a side effect no padding is added when the constant factor is equal to or larger than the width of the shift data input, also solving the reported performance bug. This fixes #4056
95 lines
2 KiB
Plaintext
95 lines
2 KiB
Plaintext
read_verilog <<EOT
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module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
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assign o = i[s*W+:W];
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$shiftx
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select -assert-count 0 t:$shiftx t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
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assign y = 1'b1 >> (w * (3'b110));
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$shr
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$shr t:$mul %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_shiftmul_2 (input [11:0] D, input [1:0] S, output [11:0] Y);
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assign Y = D >> (S*3);
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endmodule
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EOT
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prep
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design -save gold
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peepopt
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design -stash gate
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design -import gold -as gold peepopt_shiftmul_2
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design -import gate -as gate peepopt_shiftmul_2
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miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
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sat -verify -show-public -enable_undef -prove-asserts miter
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cd gate
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select -assert-count 1 t:$shr
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$shr t:$mul %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_shiftmul_3 (input [7:0] D, input [0:0] S, output [3:0] Y);
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assign Y = D >> (S*5);
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endmodule
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EOT
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prep
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design -save gold
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peepopt
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design -stash gate
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design -import gold -as gold peepopt_shiftmul_3
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design -import gate -as gate peepopt_shiftmul_3
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miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
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sat -verify -show-public -enable_undef -prove-asserts miter
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cd gate
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select -assert-count 1 t:$shr
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$shr t:$mul %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
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wire [3:0] t;
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assign t = i * 3;
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assign o = t / 3;
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 0 t:*
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