mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-05 09:04:08 +00:00
19 lines
283 B
Plaintext
19 lines
283 B
Plaintext
read_verilog -sv <<EOT
|
|
parameter A = 10;
|
|
parameter B = A;
|
|
|
|
typedef enum {
|
|
CONST_A = A,
|
|
CONST_B = A+1
|
|
} enum_t;
|
|
|
|
module top(output [3:0] q, output [3:0] r);
|
|
assign q = 10;
|
|
assign r = CONST_B;
|
|
endmodule
|
|
EOT
|
|
|
|
hierarchy -top top
|
|
sat -verify -prove q 10 top
|
|
sat -verify -prove r 11 top
|