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This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
71 lines
1.7 KiB
Verilog
71 lines
1.7 KiB
Verilog
module gate(
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off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9
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);
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input wire signed [31:0] off;
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function automatic blah(
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input x
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);
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blah = x;
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endfunction
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function automatic integer fib(
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input integer k
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);
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fib = k == 0
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? 0
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: k == 1
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? 1
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: fib(k - 1) + fib(k - 2);
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endfunction
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function automatic integer fib_wrap(
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input integer k,
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output integer o
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);
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o = off + fib(k);
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endfunction
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output integer fib0;
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output integer fib1;
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output integer fib2;
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output integer fib3;
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output integer fib4;
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output integer fib5;
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output integer fib6;
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output integer fib7;
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output integer fib8;
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output integer fib9;
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initial begin : blk
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integer unused;
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unused = fib_wrap(0, fib0);
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unused = fib_wrap(1, fib1);
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unused = fib_wrap(2, fib2);
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unused = fib_wrap(3, fib3);
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unused = fib_wrap(4, fib4);
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unused = fib_wrap(5, fib5);
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unused = fib_wrap(6, fib6);
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unused = fib_wrap(7, fib7);
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unused = fib_wrap(8, fib8);
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unused = fib_wrap(9, fib9);
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end
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endmodule
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module gold(
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off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9
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);
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input wire signed [31:0] off;
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output integer fib0 = off + 0;
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output integer fib1 = off + 1;
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output integer fib2 = off + 1;
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output integer fib3 = off + 2;
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output integer fib4 = off + 3;
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output integer fib5 = off + 5;
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output integer fib6 = off + 8;
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output integer fib7 = off + 13;
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output integer fib8 = off + 21;
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output integer fib9 = off + 34;
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endmodule
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