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https://github.com/YosysHQ/yosys
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331ac5285f
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.
56 lines
1.4 KiB
Bash
56 lines
1.4 KiB
Bash
#!/usr/bin/env bash
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trap 'echo "ERROR in chparam.sh" >&2; exit 1' ERR
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cat > chparam1.sv << "EOT"
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module top #(
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parameter [31:0] X = 0
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) (
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input [31:0] din,
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output [31:0] dout
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);
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assign dout = X-din;
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endmodule
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module top_props #(
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parameter [31:0] X = 0
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) (
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input [31:0] dout
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);
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always @* assert (dout != X);
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endmodule
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bind top top_props #(.X(123456789)) props (.*);
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EOT
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cat > chparam2.sv << "EOT"
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module top #(
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parameter [31:0] X = 0
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) (
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input [31:0] din,
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output [31:0] dout
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);
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assign dout = X-din;
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always @* assert (dout != 123456789);
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endmodule
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EOT
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if ../../yosys -q -p 'verific -sv chparam1.sv'; then
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../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
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-p 'async2sync' \
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-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
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-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
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../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
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-p 'async2sync' \
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-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
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-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
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fi
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../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
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-p 'async2sync' \
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-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
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-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
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rm chparam1.sv
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rm chparam2.sv
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