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yosys/tests/various/bug1496.ys
2024-11-05 12:36:31 +13:00

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read_rtlil << EOF
module \top
wire input 1 \A
wire output 2 \Y
cell $_AND_ \sub
connect \A \A
connect \B 1'0
connect \Y \Y
end
end
EOF
extract_fa