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yosys/tests/various/autoname.ys
2024-11-05 12:36:31 +13:00

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read_rtlil <<EOT
autoidx 2
module \top
wire output 3 $y
wire input 1 \a
wire input 2 \b
cell $and \b_$and_B
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
connect \Y $y
end
end
EOT
autoname