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22 lines
405 B
Verilog
22 lines
405 B
Verilog
module bar(clk, rst, inp, out);
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input wire clk;
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input wire rst;
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input wire inp;
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output reg out;
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always @(posedge clk)
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if (rst) out <= 1'd0;
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else out <= ~inp;
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endmodule
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module foo(clk, rst, inp, out);
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input wire clk;
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input wire rst;
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input wire inp;
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output wire out;
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bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
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endmodule
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