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17 lines
181 B
Plaintext
17 lines
181 B
Plaintext
read_verilog -icells << EOT
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module top(...);
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input [1:0] D;
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input C;
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output [1:0] Q;
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always @(posedge C)
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Q <= D;
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endmodule
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EOT
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proc
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equiv_opt -assert techmap -map +/dff2ff.v
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