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15 lines
226 B
Plaintext
15 lines
226 B
Plaintext
read_verilog -specify <<EOT
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(* abc9_box, whitebox *)
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module box(input [1:0] i, output o);
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specify
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(i *> o) = 1;
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endspecify
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assign o = ^i;
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endmodule
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module top(input [1:0] i, output o);
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box i1(i, o);
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endmodule
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EOT
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abc9 -lut 4
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