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13 lines
489 B
Systemverilog
13 lines
489 B
Systemverilog
module top (input clk, reset, antecedent, output reg consequent);
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always @(posedge clk)
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consequent <= reset ? 0 : antecedent;
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`ifdef FAIL
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test_assert: assert property ( @(posedge clk) disable iff (reset) antecedent |-> consequent )
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else $error("Failed with consequent = ", $sampled(consequent));
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`else
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test_assert: assert property ( @(posedge clk) disable iff (reset) antecedent |=> consequent )
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else $error("Failed with consequent = ", $sampled(consequent));
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`endif
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endmodule
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