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From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
16 lines
374 B
Verilog
16 lines
374 B
Verilog
module verilog_primitives (
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input wire in1, in2, in3,
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output wire out_buf0, out_buf1, out_buf2, out_buf3, out_buf4,
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output wire out_not0, out_not1, out_not2,
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output wire out_xnor
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);
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buf u_buf0 (out_buf0, in1);
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buf u_buf1 (out_buf1, out_buf2, out_buf3, out_buf4, in2);
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not u_not0 (out_not0, out_not1, out_not2, in1);
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xnor u_xnor0 (out_xnor, in1, in2, in3);
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endmodule
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