mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
7 lines
169 B
Verilog
7 lines
169 B
Verilog
module retime_test(input clk, input [7:0] a, output z);
|
|
reg [7:0] ff = 8'hF5;
|
|
always @(posedge clk)
|
|
ff <= {ff[6:0], ^a};
|
|
assign z = ff[7];
|
|
endmodule
|