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21 lines
218 B
Plaintext
21 lines
218 B
Plaintext
read_verilog <<EOT
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module top(...);
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input [3:0] A;
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input S;
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output [1:0] Y;
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wire [3:0] A1 = A + 1;
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wire [3:0] A2 = A + 2;
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assign Y = S ? A1[3:2] : A2[3:2];
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endmodule
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EOT
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proc
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alumacc
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equiv_opt -assert opt_share
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