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db5b76edc1
Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.
10 lines
199 B
Plaintext
10 lines
199 B
Plaintext
read_verilog << EOF
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module uut_00034(b, y);
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input signed [30:0] b;
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output [11:0] y = b >> ~31'b0; // shift by INT_MAX
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endmodule
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EOF
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# This should succeed, even with UBSAN halt_on_error
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opt_expr
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