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https://github.com/YosysHQ/yosys
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7f033d3c1f
Covers most of the todo list, at least functionally. Some minor issues with not always using hardware features.
29 lines
381 B
Plaintext
29 lines
381 B
Plaintext
ram distributed \RAM_LUT {
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abits 4;
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width 4;
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ifdef INIT_NONE {
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option "INIT" "NONE" {
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init none;
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}
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} else ifdef INIT_ZERO {
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option "INIT" "ZERO" {
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init zero;
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}
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} else ifdef INIT_NO_UNDEF {
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option "INIT" "NO_UNDEF" {
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init no_undef;
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}
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} else {
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option "INIT" "ANY" {
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init any;
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}
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}
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cost 4;
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port ar "R" {
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}
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port arsw "RW" {
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clock anyedge;
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}
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}
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