mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
14 lines
206 B
Verilog
14 lines
206 B
Verilog
module tb;
|
|
reg clk = 1'b0;
|
|
reg [31:0] data;
|
|
|
|
m dut(.clk(clk), .data(data));
|
|
|
|
initial begin
|
|
data = 32'haa;
|
|
#10; clk = 1; #10; clk = 0;
|
|
data = 32'haaaa;
|
|
#10; clk = 1; #10; clk = 0;
|
|
end
|
|
endmodule
|