mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
26 lines
364 B
Verilog
26 lines
364 B
Verilog
/* This is a
|
|
Multi line comment
|
|
example */
|
|
module addbit (
|
|
a,
|
|
b,
|
|
ci,
|
|
sum,
|
|
co);
|
|
|
|
// Input Ports Single line comment
|
|
input a;
|
|
input b;
|
|
input ci;
|
|
// Output ports
|
|
output sum;
|
|
output co;
|
|
// Data Types
|
|
wire a;
|
|
wire b;
|
|
wire ci;
|
|
wire sum;
|
|
wire co;
|
|
|
|
endmodule
|