mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
10 lines
106 B
Verilog
10 lines
106 B
Verilog
module wire_example( a, b, y);
|
|
input a, b;
|
|
output y;
|
|
|
|
wire a, b, y;
|
|
|
|
assign y = a & b;
|
|
|
|
endmodule
|