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yosys/tests/arch/intel_alm/blockram.ys
2024-05-03 11:32:33 +01:00

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read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
synth_intel_alm -top sync_ram_sdp -family cyclonev -noiopad -noclkbuf
cd sync_ram_sdp
select -assert-count 1 t:MISTRAL_NOT
select -assert-count 1 t:MISTRAL_M10K
select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D