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yosys/techlibs/xilinx
History
Tim 'mithro' Ansell d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
2018-04-18 16:55:12 -07:00
..
tests
.gitignore
arith_map.v
brams.txt
brams_bb.v
brams_init.py Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
brams_map.v
cells_map.v Improving vpr output support. 2018-04-18 16:55:12 -07:00
cells_sim.v Add Xilinx RAM64X1D and RAM128X1D simulation models 2018-03-07 17:31:48 +01:00
cells_xtra.sh
cells_xtra.v
drams.txt
drams_map.v
lut2lut.v
Makefile.inc Add Xilinx RAM64X1D and RAM128X1D simulation models 2018-03-07 17:31:48 +01:00
synth_xilinx.cc Improving vpr output support. 2018-04-18 16:55:12 -07:00