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21 lines
790 B
Text
21 lines
790 B
Text
read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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design -save orig
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equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 10 t:LUT4
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select -assert-none t:IB t:OB t:VLO t:LUT4 %% t:* %D
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design -load orig
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equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 6 t:LUT4
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select -assert-count 4 t:WIDEFN9
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select -assert-none t:IB t:OB t:VLO t:LUT4 t:WIDEFN9 %% t:* %D
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