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14 lines
402 B
Verilog
14 lines
402 B
Verilog
`default_nettype none
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module reversed #(parameter WIDTH=32, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
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(input wire clk,
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input wire [CTRLW-1:0] ctrl,
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input wire [DINW-1:0] din,
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input wire [SELW-1:0] sel,
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output reg [WIDTH-1:0] dout);
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localparam SLICE = WIDTH/(SELW**2);
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always @(posedge clk) begin
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dout[(WIDTH-ctrl*sel)-:SLICE] <= din;
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end
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endmodule
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