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yosys/techlibs/ice40
2019-06-13 08:24:33 -07:00
..
tests
.gitignore
abc_hx.box
abc_hx.lut
abc_lp.box Fix LP SB_LUT4 timing 2019-06-13 08:24:33 -07:00
abc_lp.lut
abc_u.box
abc_u.lut
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v
cells_sim.v Remove abc_flop{,_d} attributes from ice40/cells_sim.v 2019-06-12 09:29:30 -07:00
ice40_braminit.cc
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc
ice40_unlut.cc
latches_map.v
Makefile.inc
synth_ice40.cc