3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-14 09:55:37 +00:00
yosys/tests/arch
Emil J. Tywoniak 1907f417da tests/gatemate: update fsm LUT counts for new proc src mapping
CC_LUT2 1 (was 2), CC_L2T4 max 15 (was 14) reflect the cell mapping
produced after the proc src-location changes.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-06-24 23:55:50 +02:00
..
analogdevices WIP 2026-06-10 14:52:58 +02:00
anlogic
common
ecp5 ecp5: loosen tests 2026-05-22 18:40:01 +02:00
efinix
fabulous Cleanup 2026-04-16 11:00:44 +02:00
gatemate tests/gatemate: update fsm LUT counts for new proc src mapping 2026-06-24 23:55:50 +02:00
gowin gowin: loosen tests 2026-05-22 18:40:01 +02:00
ice40
intel_alm intel_alm: loosen tests 2026-05-22 18:40:01 +02:00
machxo2
microchip
nanoxplore
nexus nexus: loosen tests 2026-05-22 18:40:01 +02:00
quicklogic
xilinx WIP 2026-06-10 14:52:58 +02:00
generate_mk.py Move output redirect to one place 2026-04-16 11:00:44 +02:00