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yosys/techlibs/quicklogic
2021-04-17 20:54:58 +02:00
..
abc9_map.v
abc9_model.v
abc9_unmap.v
cells_sim.v
lut_sim.v
Makefile.inc
pp3_cells_map.v
pp3_cells_sim.v
pp3_ffs_map.v
pp3_latches_map.v
pp3_lut_map.v
synth_quicklogic.cc