mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-20 14:20:32 +00:00
5 lines
105 B
Verilog
5 lines
105 B
Verilog
module dffe( input clk, en, d, output reg q );
|
|
always @( posedge clk )
|
|
if ( en )
|
|
q <= d;
|
|
endmodule
|