mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-28 23:35:49 +00:00
41 lines
901 B
Text
41 lines
901 B
Text
# Test equiv_opt on narrow sub designs
|
|
|
|
read_verilog equiv_sub_narrow.v
|
|
hierarchy -top equiv_sub_mixed
|
|
proc; opt_clean
|
|
equiv_opt csa_tree
|
|
design -load postopt
|
|
select -assert-min 1 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|
|
log "equiv_sub_mixed: ok"
|
|
|
|
read_verilog equiv_sub_narrow.v
|
|
hierarchy -top equiv_sub_all
|
|
proc; opt_clean
|
|
equiv_opt csa_tree
|
|
design -load postopt
|
|
select -assert-min 1 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|
|
log "equiv_sub_all: ok"
|
|
|
|
read_verilog equiv_sub_narrow.v
|
|
hierarchy -top equiv_sub_3op
|
|
proc; opt_clean
|
|
equiv_opt csa_tree
|
|
design -load postopt
|
|
select -assert-min 1 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|
|
log "equiv_sub_3op: ok"
|
|
|
|
read_verilog equiv_sub_narrow.v
|
|
hierarchy -top equiv_sub_signed
|
|
proc; opt_clean
|
|
equiv_opt csa_tree
|
|
design -load postopt
|
|
select -assert-min 1 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|
|
log "equiv_sub_signed: ok"
|