mirror of
https://github.com/YosysHQ/yosys
synced 2026-04-22 20:03:31 +00:00
8 lines
141 B
Text
8 lines
141 B
Text
read_verilog add_1bit_wide_out.v
|
|
hierarchy -auto-top
|
|
proc; opt_clean
|
|
csa_tree
|
|
stat
|
|
|
|
select -assert-min 1 t:$fa
|
|
select -assert-count 1 t:$add
|