Emil J 4b8d42d22c Merge pull request #5095 from YosysHQ/emil/one-bit-width ... rtlil: enable single-bit vector wires		2025-05-23 15:55:45 +02:00
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aiger
aiger2
blif
btor
cxxrtl
edif
firrtl
functional
intersynth
jny
json
rtlil
simplec
smt2
smv
spice
table
verilog	Merge pull request #5095 from YosysHQ/emil/one-bit-width	2025-05-23 15:55:45 +02:00