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yosys/techlibs/intel_alm/common
History
gatecat 34a08750fa intel_alm: Fix illegal carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
..
abc9_map.v intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY 2020-07-04 19:45:10 +02:00
abc9_model.v intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF 2020-07-04 19:45:10 +02:00
abc9_unmap.v intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY 2020-07-04 19:45:10 +02:00
alm_map.v
alm_sim.v intel_alm: Fix illegal carry chains 2021-05-15 22:37:06 +01:00
arith_alm_map.v intel_alm: Fix illegal carry chains 2021-05-15 22:37:06 +01:00
bram_m10k.txt intel_alm: direct M10K instantiation 2020-07-27 15:39:06 +02:00
bram_m20k.txt
bram_m20k_map.v
dff_map.v synth_intel_alm: Use dfflegalize. 2020-07-04 22:56:16 +02:00
dff_sim.v intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
dsp_map.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
dsp_sim.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
lutram_mlab.txt
megafunction_bb.v intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
mem_sim.v intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
misc_sim.v intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
quartus_rename.v intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00