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985f4926b7
When the verilog frontend perfomed constant evaluation of unbased unsized constants in a context-determined expression it did not properly extend them by repeating the bit value. This only affected constant evaluation and not constants that made it through unchanged to RTLIL. The latter case was already covered by tests and working before. This fixes the const-eval issue by checking the `is_unsized` flag in bitsAsConst and extending the value accordingly. The newly added test also tests the already working non-const-eval case to highlight that both cases should behave the same.
28 lines
687 B
Systemverilog
28 lines
687 B
Systemverilog
module pass_through(
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input [63:0] inp,
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output [63:0] out
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);
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assign out = inp;
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endmodule
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module top;
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logic [63:0] s0c, s1c, sxc, s0d, s1d, sxd, d;
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pass_through pt(8, d);
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assign s0c = '0 << 8;
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assign s1c = '1 << 8;
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assign sxc = 'x << 8;
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assign s0d = '0 << d;
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assign s1d = '1 << d;
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assign sxd = 'x << d;
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always @* begin
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assert (s0c === 64'h0000_0000_0000_0000);
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assert (s1c === 64'hFFFF_FFFF_FFFF_FF00);
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assert (sxc === 64'hxxxx_xxxx_xxxx_xx00);
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assert (s0d === 64'h0000_0000_0000_0000);
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assert (s1d === 64'hFFFF_FFFF_FFFF_FF00);
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assert (sxd === 64'hxxxx_xxxx_xxxx_xx00);
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end
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endmodule
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