yosys/tests/verilog/genblk_port_decl.ys at 17e4383e6afa014281346d5f362972d60edd762e - mirrors/yosys - Libre-Chip.org

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Zachary Snow 1d5f3fe506 verlog: allow shadowing module ports within generate blocks

This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.

2021-02-07 11:48:39 -05:00

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 logger -expect error "Cannot declare module port `\\x' within a generate block\." 1
 read_verilog <<EOT
 module top(x);
     generate
         if (1) begin : blk
             output wire x;
             assign x = 1;
         end
     endgenerate
     output wire x;
 endmodule
 EOT