mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 19:22:31 +00:00
331ac5285f
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.
61 lines
783 B
Text
61 lines
783 B
Text
read_verilog -sv <<EOT
|
|
module Task_Test_Top
|
|
(
|
|
input a,
|
|
output reg b
|
|
);
|
|
|
|
task SomeTaskName(a);
|
|
b = ~a;
|
|
endtask
|
|
|
|
always @*
|
|
SomeTaskName(a);
|
|
|
|
assert property (b == ~a);
|
|
|
|
endmodule
|
|
EOT
|
|
proc
|
|
async2sync
|
|
sat -verify -prove-asserts
|
|
|
|
|
|
design -reset
|
|
read_verilog -sv <<EOT
|
|
module Task_Test_Top
|
|
(
|
|
input a,
|
|
output b, c
|
|
);
|
|
|
|
task SomeTaskName(x, output y, z);
|
|
y = ~x;
|
|
z = x;
|
|
endtask
|
|
|
|
always @*
|
|
SomeTaskName(a, b, c);
|
|
|
|
assert property (b == ~a);
|
|
assert property (c == a);
|
|
|
|
endmodule
|
|
EOT
|
|
proc
|
|
async2sync
|
|
sat -verify -prove-asserts
|
|
|
|
|
|
design -reset
|
|
logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
|
|
read_verilog -sv <<EOT
|
|
module Task_Test_Top
|
|
(
|
|
);
|
|
|
|
task SomeTaskName(a)
|
|
endtask
|
|
|
|
endmodule
|
|
EOT
|