yosys/tests/verilog/always_comb_nolatch_3.ys at 17e4383e6afa014281346d5f362972d60edd762e - mirrors/yosys - Libre-Chip.org

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Zachary Snow aa35f24290 sv: auto add nosync to certain always_comb local vars

If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.

2022-01-07 22:53:22 -07:00

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 read_verilog -sv <<EOF
 module top;
 logic x;
 logic z;
 assign z = 1'b1;
 always_comb begin
     logic y;
     case (x)
 'b0:
         y = 1;
     default:
         y = 0;
     endcase
     if (z)
         x = y;
     else
         x = 1'b0;
 end
 endmodule
 EOF
 proc