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69 lines
2.6 KiB
Systemverilog
69 lines
2.6 KiB
Systemverilog
module top;
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assert property ($countbits(15'b011xxxxzzzzzzzz, '0 ) == 1);
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assert property ($countbits(15'b011xxxxzzzzzzzz, '1 ) == 2);
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assert property ($countbits(15'b011xxxxzzzzzzzz, 'x ) == 4);
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assert property ($countbits(15'b011xxxxzzzzzzzz, 'z ) == 8);
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assert property ($countbits(15'b011xxxxzzzzzzzz, '0, '1 ) == 3);
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assert property ($countbits(15'b011xxxxzzzzzzzz, '1, '1, '0 ) == 3);
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assert property ($countbits(15'b011xxxxzzzzzzzz, '0, 'x ) == 5);
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assert property ($countbits(15'b011xxxxzzzzzzzz, '0, 'z ) == 9);
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assert property ($countbits(15'bz1x10xzxzzxzzzz, '0, 'z ) == 9);
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assert property ($countbits(15'b011xxxxzzzzzzzz, 'x, 'z ) == 12);
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assert property ($countbits(15'b011xxxxzzzzzzzz, '1, 'z ) == 10);
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assert property ($countbits(15'b011xxxxzzzzzzzz, '1, 'x, 'z ) == 14);
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assert property ($countbits(15'b011xxxxzzzzzzzz, '1, 'x, 'z, '0) == 15);
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assert property ($countbits(0, '0) == 32); // test integers
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assert property ($countbits(0, '1) == 0);
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assert property ($countbits(80'b0, '0) == 80); // test something bigger than integer
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assert property ($countbits(80'bx0, 'x) == 79);
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always_comb begin
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logic one;
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logic [1:0] two;
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logic [3:0] four;
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// Make sure that the width of the whole expression doesn't affect the width of the shift
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// operations inside the function.
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one = $countbits(3'b100, '1) & 1'b1;
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two = $countbits(3'b111, '1) & 2'b11;
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four = $countbits(3'b111, '1) & 4'b1111;
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assert (one == 1);
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assert (two == 3);
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assert (four == 3);
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end
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assert property ($countones(8'h00) == 0);
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assert property ($countones(8'hff) == 8);
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assert property ($countones(8'ha5) == 4);
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assert property ($countones(8'h13) == 3);
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logic test1 = 1'b1;
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logic [4:0] test5 = 5'b10101;
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assert property ($countones(test1) == 1);
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assert property ($countones(test5) == 3);
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assert property ($isunknown(8'h00) == 0);
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assert property ($isunknown(8'hff) == 0);
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assert property ($isunknown(8'hx0) == 1);
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assert property ($isunknown(8'h1z) == 1);
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assert property ($isunknown(8'hxz) == 1);
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assert property ($onehot(8'h00) == 0);
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assert property ($onehot(8'hff) == 0);
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assert property ($onehot(8'h01) == 1);
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assert property ($onehot(8'h80) == 1);
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assert property ($onehot(8'h81) == 0);
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assert property ($onehot(8'h20) == 1);
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assert property ($onehot0(8'h00) == 1);
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assert property ($onehot0(8'hff) == 0);
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assert property ($onehot0(8'h01) == 1);
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assert property ($onehot0(8'h80) == 1);
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assert property ($onehot0(8'h81) == 0);
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assert property ($onehot0(8'h20) == 1);
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endmodule
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