mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 19:22:31 +00:00
41 lines
984 B
Text
41 lines
984 B
Text
read_verilog << EOT
|
|
|
|
module ff4(...);
|
|
parameter [0:0] CLK_INV = 1'b0;
|
|
parameter [3:0] DATA_INV = 4'b0000;
|
|
(* invertible_pin = "CLK_INV" *)
|
|
input clk;
|
|
(* invertible_pin = "DATA_INV" *)
|
|
input [3:0] d;
|
|
output [3:0] q;
|
|
endmodule
|
|
|
|
module inv(...);
|
|
output o;
|
|
input i;
|
|
endmodule
|
|
|
|
module top(...);
|
|
input d0, d1, d2, d3;
|
|
input clk;
|
|
output q;
|
|
ff4 #(.DATA_INV(4'h5)) ff_inst (.clk(clk), .d({d3, d2, d1, d0}), .q(q));
|
|
endmodule
|
|
|
|
EOT
|
|
|
|
extractinv -inv inv o:i
|
|
clean
|
|
|
|
select -assert-count 2 top/t:inv
|
|
select -assert-count 2 top/t:inv top/t:ff4 %ci:+[d] %ci:+[o] %i
|
|
|
|
select -assert-count 1 top/t:inv top/w:d0 %co:+[i] %i
|
|
select -assert-count 0 top/t:inv top/w:d1 %co:+[i] %i
|
|
select -assert-count 1 top/t:inv top/w:d2 %co:+[i] %i
|
|
select -assert-count 0 top/t:inv top/w:d3 %co:+[i] %i
|
|
|
|
select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i
|
|
select -assert-count 1 top/t:ff4 top/w:d1 %co:+[d] %i
|
|
select -assert-count 0 top/t:ff4 top/w:d2 %co:+[d] %i
|
|
select -assert-count 1 top/t:ff4 top/w:d3 %co:+[d] %i
|