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33 lines
736 B
Verilog
33 lines
736 B
Verilog
`default_nettype none
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module func_block_top(inp, out1, out2, out3);
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input wire [31:0] inp;
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function automatic [31:0] func1;
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input [31:0] inp;
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reg [31:0] idx;
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for (idx = 0; idx < 32; idx = idx + 1) begin : blk
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func1[idx] = (idx & 1'b1) ^ inp[idx];
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end
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endfunction
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function automatic [31:0] func2;
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input [31:0] inp;
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reg [31:0] idx;
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for (idx = 0; idx < 32; idx = idx + 1) begin : blk
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func2[idx] = (idx & 1'b1) ^ inp[idx];
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end
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endfunction
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function automatic [31:0] func3;
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localparam A = 32 - 1;
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parameter B = 1 - 0;
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input [31:0] inp;
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func3[A:B] = inp[A:B];
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endfunction
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output wire [31:0] out1, out2, out3;
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assign out1 = func1(inp);
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assign out2 = func2(inp);
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assign out3 = func3(inp);
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endmodule
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