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https://github.com/YosysHQ/yosys
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64 lines
No EOL
2 KiB
Text
64 lines
No EOL
2 KiB
Text
# ISC License
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#
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# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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read_verilog <<EOT
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module ram_TDP (clka,clkb,wea,addra,dataina,qa,web,addrb,datainb,qb);
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parameter addr_width = 10;
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parameter data_width = 2;
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input clka,clkb,wea,web;
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input [data_width - 1 : 0] dataina,datainb;
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input [addr_width - 1 : 0] addra,addrb;
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output reg [data_width - 1 : 0] qa,qb;
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reg [addr_width - 1 : 0] addra_reg, addrb_reg;
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reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
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always @ (posedge clka)
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begin
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addra_reg <= addra;
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if(wea) begin
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mem[addra] <= dataina;
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qa <= dataina;
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end else begin
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qa <= mem[addra];
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end
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end
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always @ (posedge clkb)
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begin
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addrb_reg <= addrb;
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if(web) begin
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mem[addrb] <= datainb;
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qb <= datainb;
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end else begin
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qb <= mem[addrb];
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end
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end
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endmodule
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EOT
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synth_microchip -top ram_TDP -family polarfire -noiopad
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select -assert-count 1 t:RAM1K20
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select -assert-none t:RAM1K20 %% t:* %D
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# similar to ram_TDP.v, but different write mode and read_enable=~write_enable
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design -reset
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read_verilog ../common/blockram.v
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hierarchy -top sync_ram_tdp
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chparam -set DATA_WIDTH 2 -set ADDRESS_WIDTH 10
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synth_microchip -top sync_ram_tdp -family polarfire -noiopad
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select -assert-count 1 t:RAM1K20
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select -assert-count 2 t:CFG1
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select -assert-none t:RAM1K20 t:CFG1 %% t:* %D |