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https://github.com/YosysHQ/yosys
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42 lines
1.3 KiB
Text
42 lines
1.3 KiB
Text
# 512 x 40 bit -> CC_BRAM_20K SDP RAM
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 40 sync_ram_sdp
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synth_gatemate -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:CC_BUFG
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select -assert-count 1 t:CC_BRAM_20K
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# 512 x 20 bit x 2 -> CC_BRAM_20K TDP RAM
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design -reset
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 20 sync_ram_tdp
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synth_gatemate -top sync_ram_tdp -noiopad
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select -assert-count 2 t:CC_BUFG
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select -assert-count 1 t:CC_BRAM_20K
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# 512 x 80 bit -> CC_BRAM_40K SDP RAM
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design -reset
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 80 sync_ram_sdp
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synth_gatemate -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:CC_BUFG
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select -assert-count 1 t:CC_BRAM_40K
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# 512 x 40 bit -> CC_BRAM_20K SDP ROM
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design -reset
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read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 40 sync_rom
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synth_gatemate -top sync_rom -noiopad
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cd sync_rom
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select -assert-count 1 t:CC_BUFG
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select -assert-count 1 t:CC_BRAM_20K
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# 512 x 80 bit -> CC_BRAM_40K SDP ROM
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design -reset
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read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 80 sync_rom
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synth_gatemate -top sync_rom -noiopad
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cd sync_rom
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select -assert-count 1 t:CC_BUFG
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select -assert-count 1 t:CC_BRAM_40K
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